1. Technical Field
The present invention relates in general to data processing and, in particular, to a processor and method for fetching data from memory. Still more particularly, the present invention relates to a processor and method for prefetching data from memory based upon a detected stride.
2. Description of the Related Art
As processor clock frequencies have continued to increase, thereby permitting increased instruction throughput, memory latency has become a principal impediment to improved processor performance. Although instructions are commonly speculatively fetched from memory in order to ameliorate the effects of instruction access latency, in a conventional processor data is fetched from memory only after a load instruction has been executed to determine the address of the data to be fetched (i.e., only demand fetching is used).
The present invention includes a recognition that in order to reduce data access latency, it is desirable to intelligently prefetch data from memory.
It is therefore one object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved processor and method for fetching data from memory.
It is yet another object of the present invention to provide a processor and method for prefetching data from memory based upon a detected stride.
The foregoing objects are achieved as is now described. According to the method of the present invention, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request. The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.